CCD image sensors typically include an array of photosensitive areas that collect charge carriers in response to illumination. The collected charge is subsequently transferred from the array and converted to a voltage from which an image may be reconstructed by associated circuitry. FIG. 1A depicts a conventional interline CCD image sensor 10 that contains an array of photodiodes 11 arranged in columns. A vertical CCD (VCCD) 12 is disposed next to each column of photodiodes 11, and the VCCDs 12 are connected to a horizontal CCD (HCCD) 13. Each photodiode 11 along with a “vertical channel,” i.e., its corresponding portion of VCCD 12, constitutes a “pixel” of the image sensor 10. Following an exposure period, charge is transferred from the photodiodes 11 into the VCCDs 12, which subsequently shift the charge, row-by-row in parallel, into the HCCD. The HCCD then transfers the charge serially to output circuitry 14 that includes, e.g., a floating diffusion sense node and an output buffer amplifier. The charge from the HCCD is converted, pixel-by-pixel, into voltage at the output circuitry 14, and the signal is then transferred to additional circuitry (either on-chip or off-chip) for reconstruction into an image.
Over time, CCD image sensors have grown larger (i.e., incorporated more pixels) and have been utilized in a host of applications, some of which demand high frame rates, e.g., machine vision applications and video display. While innovative CCD image sensor designs incorporating, e.g., multiple output circuits, have enabled higher frame rates, such designs often cannot provide performance increases commensurate with growing sensor sizes. Furthermore, many CCD image sensors having multiple output circuits utilize HCCDs having individual shift registers of different sizes, which can increase complexity and compromise the charge capacity of the HCCD. Thus, there is a continuing need for CCD image sensors having multiple outputs, with their concomitant increase in frame rate, as well as straightforward, easily fabricated layouts that do not deleteriously impact charge-handling capacity.